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100MHz Clock Power Divider

The 100MHz clock power divider is a low noise, high stability power divider with power amplification capability. It is widely applicable in areas such as RF component research and development, industrial production, and laboratory fundamental research.

100MHz Clock Power Divider

Features

01

Input frequency of 100MHz，supports customizable frequencies.

02

1 input channel, 20 output channels.

03

Typical gain of output signal : 2dB.

04

Phase difference fluctuations between channels: ≤0.2° (within a temperature change of 5℃).

05

Phase noise:≤-130dBc/Hz@100Hz；≤-160dBc/Hz@1kHz.

Specifications

Number of output channels20
Input frequency100MHz
Harmonic suppression≥60dBc
Channel isolation≥35dBc
Phase noise≤-130dBc/Hz@100Hz；
≤-160dBc/Hz@1kHz
Typical gain of output signal2dB
Input signal P1dB-in≥4.5dBm
Phase difference between channels≤0.2°(within a temperature change of 5℃)